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Samsung, TSMC and Intel team up to develop chip stacking technology

The world’s three largest chipmakers announced the formation of a consortium to collaborate on next-generation chip stacking technology.

Samsung, TSMC, and Intel team up to develop chip stacking technologies

In the next major battle in the drive to manufacture more powerful electronics, Intel and Samsung will collaborate to create an industry standard for improved chip stacking technology.

On Thursday, the world’s three largest chipmakers, as well as a number of other leading tech firms, announced the formation of a consortium to collaborate on next-generation chip packaging and stacking, the final steps in semiconductor manufacturing, prior to the chips being mounted on printed circuit boards and being installed into electronic devices.

The unprecedented collaboration of the world’s top chipmakers demonstrates how critical these technologies have become in the industry. The consortium will include top global chip makers and IT companies such as Arm, Qualcomm, and Advanced Micro Devices, as well as Microsoft, Meta, Google Cloud, and ASE Technology Holdings.

More firms are welcome to join the group, according to the organisation.

Chip packaging was once thought to be less important and technologically challenging than chip production. However, as the world’s biggest chipmakers, Samsung, Intel, and TSMC, compete in manufacturing even more powerful processors, the sector has emerged as a crucial battlefield.

Until now, semiconductor development has mostly concentrated on how to cram more transistors onto a chip; in general, more transistors equal more processing capability. However, as the spacing between transistors has been reduced to just a few nanometers, this method has become more difficult, prompting some to predict the end of Moore’s law, which states that after every two years, the transistors used in a chip are doubled.

As a result, the most effective technique to pack and stack small chips with varied functions and features has become a major focus for most chipmakers.

The aim of the consortium is to develop a new ecosystem and stimulate collaboration within the packaging and stacking segments by establishing a common chip packaging standard, named Universal Chiplet Interconnect Express (UCIe). A more powerful chip system can be created via better means of mixing several types of chips, or chiplets in one package.

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